
LDS8846
BLOCK DIAGRAM
Figure 2. LDS8846 Functional Block Diagram
BASIC OPERATION
The device starts operating if the EN pin is set logic
HIGH and input voltage is higher that under voltage
protection lockout threshold.
The low dropout PowerLite ? Current regulator
performs well at input voltages up to 50 mV greater
than the LED forward voltage significantly increasing
the driver’s efficiency.
ILED, mA
5
10
15
20
25
30
R SET , k Ω
96
48
32
24
19.2
16
Nearest standard 1% value
95.3
47.5
31.6 or 32.4
23.7 or 24.3
19.1
15.8 or 16.2
? 400 x
I
, where V SET =1.2V, and R SET is
R SET
Input pins EN, CTRL0, CTRL1, and CTRL2 may be
either logic LOW or HIGH during power-up. However,
logic voltage should never exceed input voltage V IN ,
and these pins should not be left float.
LED Current Setting
The desired current value in each of the four LED is
set by external resitor R SET connevted between I SET
pin and ground..
The LED current is 400 times greater than the current
through R SET and can be estimated (in mA) by
following equation:
V SET
LED
its resistance in kohms.
R SET value for typical I LED current is shown at the
table below.
The average current value may be decreased using
PWM signal applied to either CTRL0, CTRL1 or
CTRL2 pin. The LDS8846 allows modulation
frequiencies in the range from 100 Hz to 5 kHz with
duty cycles from 100% to 1% and from 5 kHz to 30
kHz with duty cycles from 100% to 10%. Modulation
frequiencies lower than 100 Hz are not
recommended especialy at short duty cycles because
LED flicker may be visible.
If CTRL1 and CTRL2 pins are logic HIGH and PWM
signal applies to CTRL0 pin, then all four LEDS are
dimming synchronously.
If CTRL0 and CTRL2 pins are logic HIGH and PWM
signal applies to CTL1 pin, then LEDs from LED1 to
LED3 are dimming, while LED4 is always off.
? 2009 IXYS Corp.
Characteristics subject to change without notice
6
Doc. No. 8846DS, Rev. N1.6